FPGA-Based Image Processor for Sensor Nodes in a Sensor Network

Masaki Yoshimura, Hideki Kawai, Taketoshi Iyota, Yongwoon Choi
Faculty of Engineering, Soka University, 1-236 Tangimachi Hachioji, Tokyo, Japan

© 2009 Yoshimura et al.

open-access license: This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 International Public License (CC-BY 4.0), a copy of which is available at: This license permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.

* Address correspondence to this author at the Kasetsart Agricultural and Agro-Industrial Product Improvement Institute (KAPI), Kasetsart University, 50, Chatuchak, Bangkok, 10900, Thailand; Tel./Fax. 66-2942- 8599; E-mail:


A field-programmable-gate-array- (FPGA-) based image processor which can be used for sensor nodes in a sensor network has been proposed and developed. Image processors for the nodes must satisfy requirements such as low power consumption, small circuitry scale, and modifiability of the hardware architecture. By developing an image processor designed using an FPGA, SRAM modules, and the vector code correlation method which is suitable for the construction of the target hardware architecture, it was possible to ensure that the processor satisfies these requirements. In this paper, we present the details of this image processor, which employs the template matching method for target tracking as well as the background subtraction method for object extraction. In addition, in order to verify its applicability in sensor nodes, we demonstrate the usefulness of the image processor from the results of an experiment in which the template matching and background subtraction methods were implemented simultaneously.

Keywords: FPGA-based image processor, Sensor network, Template matching, Background subtraction, Real-time processing, Low power consumption.